Sigma-delta modulators (sometimes referred to as delta-sigma modulators) have been used in analog-to-digital converters for some time. The reader is referred to the following technical articles incorporated herein by reference.
1) "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", J. C. Candy, IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-22, No. 3, pp. 298-305, March 1974 PA0 2) "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator", J. C. Candy, et al., IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-24, No. 11, pp. 1268-1275, November 1976 PA0 3) "A Use of Double Integration in Sigma Delta Modulation", J. C. Candy, IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-33, No. 3, pp. 249-258, March 1985
Substantial effort has been made by specialists in the field of oversampled converter design to develop plural-order sigma-delta modulators, so as to obtain higher resolution for a given oversampling ratio R. Inasfar as this specification is concerned, the order of a sigma-delta modulator stage corresponds to how many times the error between its output and input signals (including quantization noise) is integrated with respect to time in the overall feedback loop used for determining that error. A sigma-delta modulator stage supplies its output signal from a quantizer (or analog-to-digital converter) of the integrated error, which signal is converted to an analog signal by a digital-to-analog converter included together with the quantizer within the stage. The analog signal from the digital-to-analog converter is compared to the analog input signal to the sigma-delta modulator stage to generate the error signal that is integrated with respect to time in order to close the overall feedback loop. In a second-order sigma-delta modulator stage there is another feedback loop inside the overall feedback loop. In this other loop the output signal as converted to analog form is compared to the error between the output and input signals of the stage as once integrated, thereby to generate another error signal, which is further integrated to generate the input signal for the quantizer. The order of a sigma-delta converter, which converter includes cascaded sigma-delta modulator stages followed in cascaded by a decimating filter, is the sum of the orders of the cascaded sigma-delta modulator stages included therein.
The ordinal number of a sigma-delta modulator stage within a plural-stage sigma-delta converter, on the other hand, is determined directly by how many sigma-delta modulator stages the input signal to the converter must pass through to reach the output connection of that sigma-delta modulator stage.
Most sampled-data sigma-delta converters filter the quantization noise spectrum with a system function N(z) that is simply differentiation by discrete time --i.e., N(z)=(1-z.sup.-1).sup.L, where L refers to the order of the sigma-delta modulator. Customarily, sigma-delta converters provide what is referred to as "sinusoidal" shaping of quantization noise, wherein the quantization noise previous to shaping by convolution with N(z) is assumed to be white--i.e., to exhibit a broad-band flat response. This allows the output noise spectrum to be approximated by EQU S.sub.N (.omega.T)=K.sub.QN [2 sin(.omega.T/2)].sup.2L,
where K.sub.QN is the power-spectral-density (PSD) of the unshaped quantization noise. The final noise, accompanying the response of the decimation filtering which follows the sigma-delta modulator, is determined by integrating S.sub.N (.omega.T) over the baseband--i.e., from .omega.=0 to .omega.=.pi./R. Using this noise level, the theoretically attainable resolution, B, of a sigma-delta converter with the customary sinusoidal noise shaping can be expressed in terms of bits as follows: EQU B=(L+0.5) log.sub.2 R-log.sub.2 [.pi..sup.L (2L+1).sup.-0.5 ]+(P-1).
Resolution as so expressed increases by one bit per octave of oversampling for each integer increment in modulator order L.
The number of bits resolution obtained, B, is linearly related to P, the number of quantizer bits used in the sigma-delta modulator. It is desirable, then, to be able to use multiple-bit quantization in the sigma-delta modulator, in order to increase overall resolution in the oversampling converter. However, the accuracy of the digital-to-analog converter (DAC) in the quantizer must be consistent with the level of performance of the oversampled ADC after decimation, or else resolution is limited to less than that theoretically attainable.
To avoid the problems of nonlinearity in the DACs, the common practice is to use single-bit DACs after single-bit quantizers, or ADCs, in sigma-delta modulators. In such configurations errors in the two levels of DAC output can introduce gain errors or offset errors, or both. However, the linearity of the converter is never compromised since a straight line invariably will fit through just two points.
If one seeks to introduce a four-bit quantizer into a sigma-delta modulator, then the DAC used after the quantizer must respond to respective ones of the four-bit digital numbers from the quantizer to generate sixteen points of output signal level through which a straight line may thread without any point exhibiting more than a specified departure from the line. That specified departure is just smaller than one-half the increment (or decrement) in that four-bit quantizer output signal level which causes the smallest resolvable increment (or decrement) in the ultimate digital output signal of the complete converter. Otherwise, as known to those highly skilled in the art, the desired resolution of the converter will not be available in certain portions of the range of the analog input signal to the sigma-delta modulator (i.e., those portions of the range where points are most remote from the best-fitting straight line). Obtaining such accuracy from a DAC is difficult, even with trimming, tending to make a four-bit quantizer expensive to realize in the normal monolithic integrated circuit construction. Then, too, a four-bit quantizer takes up considerably more area on a monolithic integrated circuit die than a single-bit quantizer does.
In the context of a plural-order sigma-delta modulator, the plural use of four-bit quantizers compounds these shortcomings.
This observation leads to a consideration of oversampling converters having sinusoidal noise shaping which are of a type using a plural-order sigma-delta modulator in which only one or at most a few of the sigma-delta modulator stages incorporates a quantizer with multiple-bit resolution that is higher than the resolution of each quantizer in other of the sigma-delta modulator stages. This avoids multiplying the problems associated with using a quantizer with multiple-bit resolution.